Asynchronous Circuit Design and Verification

Asynchronous Circuit Design and Verification

Former research area

Supported by grants from the National Science Foundation (NSF CAREER award MIP-9625014), Intel Corporation, the Semiconductor Research Corporation (SRC), and the State of Utah, Professor Myers and his graduate students developed the ATACS tool for the synthesis and verification of timed asynchronous circuits. ATACS was utilized during the Intel RAPPID project which resulted in a prototype VLSI chip that was 3 times faster while using only half the power of the comparable synchronous design. NSF Japan Program award INT-0087281 helped foster a collaboration between the PI and Professor Tomohiro Yoneda of the National Institute of Informatics in Tokyo which has resulted in over 30 publications to date.

Contributors

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Curt Nelson

Walla Walla University, Professor, Retired

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David Walter

Amazon (AWS S3), Senior SDE

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Eric Mercer

Brigham Young University, Associate Professor

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Eric Peskin

Yale University, Director of High-Performance Computing

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Hans Jacobson

IBM T. J. Watson Research Center, Researcher

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Robert Thacker

AMD, MTS Silicon Design Engineer

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Scott Little

Maxim Integrated, EDA

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Wendy Belluomini

IBM, Director of AI and Cognitive Software

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Brandon Bachman

Intel, Engineering Technology Development Manager

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Chris Krieger

University of Maryland, Laboratory for Physical Sciences, Lead researcher

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Dhanashree Kulkarni

Intel Technologies, Analog Engineer

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Kip Killpack

Intel, System Architect

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Yanyi Zhao

Juniper Networks, Program Manager

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Nick Seegmiller

Amazon, Software Development Manager

Publications